Generally a silicon wafer manufacturing method comprises, as shown in FIG. 18(a), a slicing step 100 of slicing a single crystal ingot to obtain a thin disk-shaped wafer; a chamfering step 102 of chamfering a peripheral edge portion of the wafer obtained through the slicing step 100 to prevent cracking and chipping of the wafer; a lapping step 104 of flattening this wafer; an etching step 106 of removing processing deformation remaining in the so chamfered and lapped wafer; a polishing step 108 of making a mirror surface of the wafer; and a cleaning step 110 of cleaning the polished wafer to remove a polishing agent or dust particles deposited thereon. The main steps are only listed above, and sometimes other steps such as a heat treatment step and a surface grinding step may be added, or the step sequence may be changed.
The polishing step 108 of making a mirror surface of the wafer is further classified into sub-steps, and various types of polishing methods and polishing apparatus are used in each of the sub-steps. As a wafer single side polishing apparatus 200 used in the polishing process, for instance, as shown in FIG. 14, there has been widely known a polishing apparatus comprising a disk-shaped turn table 206 which is rotated by a rotary shaft 204 and has a polishing cloth 202 adhered on the upper surface thereof, a wafer holding head (polishing head) 208 for holding one surface of a wafer (W) to be polished and contacting another surface of the wafer (W) to the polishing cloth 202, and a head driving mechanism 210 for operating relative rotation of the wafer holding head 208 against the turn table 206, wherein the wafer is polished by supplying slurry 214 containing abrasive grains from a slurry supplying unit 212 between the polishing cloth 202 and the wafer (W).
As another type of polishing, as shown in FIG. 15, there is a method of simultaneously polishing both the front and back surfaces of a wafer. This double side polishing apparatus 220 has a lower polishing turn table 222 and an upper polishing turn table 224 which are faced each other vertically. A lower polishing cloth 226 is adhered on the upper surface of the lower polishing turn table 222, and an upper polishing cloth 228 is adhered on the lower surface of the upper polishing turn table 224.
A disk-shaped carrier 230 is supported between the upper surface of the lower polishing cloth 226 of the lower polishing turn table 222 and the lower surface of the upper polishing cloth 228 of the upper polishing turn table 224 and rotates and revolves slidably between the lower polishing cloth 226 and the upper polishing cloth 228. The carrier 230 has a plurality of wafer holes 232.
Wafers (W) to be polished are set in the wafer holes 232. When the wafers (W) are polished, a polishing agent is supplied between the wafers (W) and the polishing cloths 226, 228 via throughholes (not shown) formed in the upper polishing turn table 224 from nozzles (not shown). As the carrier 230 rotates and revolves, the wafers (W) rotate and revolve slidably between the lower polishing cloth 226 and the upper polishing cloth 228, thereby both the surfaces of the wafers (W) being polished.
There are also various methods of holding a wafer. For instance, there are a batch holding method in which a plurality of wafers are adhered on one and the same plate using wax or the like and are polished, and a single wafer holding method in which wafers are held one by one by means of wax or vacuum chucking and are polished.
The wafer holding method employed when polishing a wafer is divided broadly into two systems, that is, a wax mounting system and a waxless system. The waxless system comprises a vacuum chucking system, a template system, and the like.
Of these systems, as shown in FIG. 17, a wafer holding head 240 according to the template system has such a structure as, when polishing a wafer (W), the wafer (W) is fitted in an engagement hole 244 in a template blank of the template 242, and the back surface of the wafer (W) is held by a backing pad 250 adhered to a lower surface of the upper polishing turn table 248 attached to a lower end of a head 246.
When polishing wafers (W) with the holding head 240, wafers to be polished are fitted into each of the engagement holes 244 in the template blank of the template 242, respectively, and the thus situated template 242 is arranged on a lower polishing turn table (not shown) so that the wafers (W) are in lower positions. In this state, one surface of the wafer (W) contacts a polishing cloth adhered on the lower polishing turn table (not shown). In this state, when a back pressure is applied to the template 242 by the upper polishing turn table 248 and at the same time the lower polishing plate (not shown) is rotated, the template 242 rotates at the place together with the lower polishing plate and the wafer (W) is polished.
Thus there is known a holding method named a waxless system in which, without using vacuum chucking or adhesion by wax, a soft material named a backing pad is used for holding a wafer. Also there is a polishing method named CMP (Chemical and Mechanical Polishing) in which a wafer is polished in such a manner as the wafer is held by a soft backing pad not to transfer a vacuum chucking side configuration of the wafer to a front surface thereof.
With a combination of various types of polishing apparatus described above, a wafer is mirror polished by multistage polishing including primary polishing, secondary polishing, final polishing, and the like.
Currently, the wax mounting system is often used in the above mentioned polishing systems, but in view of deterioration of a flatness level due to variations in an adhesive layer, cleaning of the wax, and so forth, for instance, polishing of the waxless system, double side polishing or the like have also been employed. For instance, as shown in FIG. 18(b), a waxless polishing step 108A shows a case in which polishing of the waxless system is performed in all of a primary polishing step (A1), a secondary polishing step (A2), and a final polishing step (A3), while a double side polishing step 108B shows a case in which double side polishing is performed in a primary polishing step (B1) and polishing of other systems are employed in a secondary polishing step (B2) and a final polishing step (B3).
The primary polishing step (A1), (B1) is for the main purpose of flattening and making a mirror surface, and is a step of polishing a wafer with the stock removal of 10 μm or more. A relatively hard polishing cloth may be used for correcting a wafer configuration (so-called correction polishing). Recently, before a polishing step, a flatness level of a wafer is improved by, for instance, an etching step, a lapping step prior to the etching step, or a surface grinding step, and with keeping this improved configuration, making a mirror surface (so-called copy polishing) may be performed. The combination of correction polishing and copy polishing may improve a flatness level of a wafer and make a mirror surface thereof.
The secondary polishing step (A2), (B2) is for the main purpose of making a mirror surface of the portion which has not been improved in the primary polishing step (A1), (B1), and in the secondary polishing step, there is mainly performed so-called copy polishing wherein a wafer is polished with keeping a wafer configuration by removing a certain thickness with the stock removal of several μm. In this stage, there are some cases where a configuration of a peripheral portion of a wafer is corrected.
The final polishing step (A3), (B3) is for the purpose of improving haze, and the stock removal is of a very small amount.
In order to improve a flatness level more by removing tapers and the like of a wafer, it is effective to polish the wafer while rotating it during the polishing operation, and the waxless polishing or the double side (simultaneous) polishing is preferable. Therefore, these systems of polishing may be performed in the primary polishing step and so on.
When a wafer is polished by the conventional waxless polishing or double side (simultaneous) polishing, although tapers are improved, a number of peripheral sags are generated. Further while the wafer is polished in multiple polishing stages, rises and the like are generated to form inflection points on a wafer surface, especially in peripheral portions thereof, and make irregularities in a minute area (may be termed nanotopology) or flatness thereof worse.
The peripheral sags described above are due to a phenomenon wherein the periphery of the wafer is polished excessively and becomes thinner than the central portion thereof in terms of thickness. This phenomenon easily occurs when polishing a wafer by a general method.
The rises are due to a phenomenon wherein the periphery of the wafer is not polished and becomes thicker than the central portion. This phenomenon seldom occurs usually, but often occurs when a wafer is polished with a polishing head using a retainer ring in CMP and the like.
The rises may also be generated when the polishing rate is intentionally slowed down in the wafer periphery by, for instance, making the polishing pressure lower only in the periphery than in the central portion to improve the flatness level in the primary or secondary polishing step (on the assumption that peripheral sags are generated).
The inflection points are formed when a wafer having the peripheral sags is polished in the above described manner that the rises are generated. The presence of the inflection points makes the value termed nanotopology worse.
The nanotopology (may be also termed nanotopography) is one of surface evaluation wherein a wafer surface is divided into a plurality of areas and a variation in undulations (peak to valley: PV value) for each of the areas is evaluated. The evaluation is carried out as to whether what percentage of the wafer surface is occupied by the areas having the specified variation in undulations (PV value) or what extent is the maximum PV value among the PV values for all the evaluated areas.
The flatness is based on a back side reference, a front side reference, etc., and expressed, for instance, as SBIR or SFQR. Here, the SBIR (Site Back side Ideal Range) is defined as a difference in the distance between the highest position and the lowest position from a vacuum chucking face which vacuum chucks and fixes a wafer, when assuming the chucking face as a fixed reference for flatness and evaluating each site (each area obtained by dividing the entire surface of a wafer into respective prescribed areas).
On the other hand, the SFQR (Site Front least-sQuares Range) is a value expressing a maximum range of irregularities against an average plane of a front side reference in terms of flatness, the average plane being calculated for each site. As to the wafer flatness, it is necessary to improve the SFQR and nanotopology of the front side reference.
When a wafer is subjected to the double side polishing only, although an inflection point is not formed, sags are easily generated in the periphery of the wafer. Especially, the sags are generated on both surfaces of the wafer, and hence there is a big effect thereof. Although the sags can be made smaller by reducing a stock removal in the double side polishing step, in order to make a mirror surface a larger stock removal is required in the subsequent secondary polishing step, and large sags are generated after all. Also when a wafer is subjected to polishing of the waxless system, sags are easily generated in the periphery of the wafer as in the case of double side polishing, and the flatness level is not sufficient.